The invention relates to peak detectors and, in particular, to peak detectors for detecting and filtering the peak value of a generally arbitrary signal waveform in the presence of noise.
In integrated circuit radio frequency (RF) receivers employing pulsed ON-OFF RF amplitude signaling (also referred to as ON-OFF Keyed or OOK signaling), the received signal must be detected in the presence of noise in the communication channel. FIG. 1 illustrates waveforms of a signal being modulated for transmission on a communication channel. Referring to FIG. 1, signal waveform 10 denotes the data to be transmitted (TX data) as a series of zero""s and one""s. When OOK signaling is used to transmit the data, the amplitude of the RF carrier signal is modulated by the TX data which has the result of turning off the RF carrier signal when the data is a xe2x80x9czeroxe2x80x9d value and turning on the RF carrier signal when the data is a xe2x80x9conexe2x80x9d value. The transmitted signal is illustrated by signal waveform 12. The noise presence in the communication channel is depicted by signal waveform 14 which noise is superimposed on the transmitted signal during transmission. The result is that the signal received by a receiver (signal waveform 16) contains the transmitted signal distorted by noise.
To decode the data contained in the received signal, the receiver must discriminate between the strength of the received signal in the presence of background noise. Generally, the receiver needs to detect the amplitude of the received signal including the noise component and determine when a data signal is present. Methods for detecting an OOK modulated signal are known and generally involve detecting the peak value of the received signal over a defined time period. By comparing changes in the peak value of the received signal, it is possible to identify when a valid signal has been received.
To improve the likelihood of detecting a valid signal, filtering techniques are generally used with the peak detector to mitigate the effects of background noise. To make filtering effective, all a priori knowledge of the transmitted signal must be used to design the filter for optimum system performance. FIGS. 2 and 3 illustrate two examples where different filter characteristics are employed to detect the received signal.
FIG. 2 illustrates the signal waveforms of transmitted and received signals where the goal is to recover data transmitted in OOK format. In this case, the time constant of the filter used in the receiver is designed to have equal attack and decay characteristics so that the filter responds to the signal content at the transmitted data rate but rejects spurious noise. Filtered signal 22 depicts the signal waveform recovered from the received signal 20 where the content of the transmitted data (signal 18) is correctly identified.
FIG. 3 illustrates the signal waveforms of transmitted and received signals where the filter of the receiver is intended to help identify which receive channel should be selected to recover transmitted data from. That is, the detector is operating as a signal detector only. In this case, the filter in the receiver should be designed to have a faster attack characteristic and a slower decay characteristic since the data pattern may not be repetitive, that is, the transmitted data may have unequal mark-space ratios. A fast-attack-slow-decay filter characteristic helps to select and hold the correct receive channel provided the transmitted data is of sufficient mark-space ratio for the chosen filter decay characteristic. As shown in FIG. 3, the filtered signal 28 identifies the receive channel of the transmitted data 24 when transmitted data 24 has unequal mark-space ratios. The two examples shown in FIGS. 2 and 3 demonstrate that different applications require different filter characteristics associated with the peak detect circuitry.
Conventional peak detectors in integrated circuits are usually built using linear filters and have several disadvantages. For example, large time constant linear filters require very small currents, large resistors and large capacitors which consume too much chip area in integrated circuits, thereby increasing cost and lowering yield. Also, it is difficult to provide linear filters which can be programmed for different filter characteristics without consuming large chip area using redundant switchable circuitry. Finally, linear filter performance often suffers from operational temperature and voltage variation or fabrication process drift so that large variation in filter characteristics may result from the use of linear filters.
FIG. 4 illustrates a conventional peak detector circuit. Peak detector 30 includes a diode D receiving the input signal to be processed. Diode D rectifies the input signal and the peak value (Vpk) of the rectified input signal is stored on a capacitor Cap. A resistor Rdecay is coupled to the peak voltage node to provide a decay path to discharge capacitor Cap and reset the peak voltage value when needed. Typically, additional filtering functions are provided to smooth out the Vpk signal, such as by using an RC filter network. The output signal is thus a filtered version of the Vpk signal. When a more controlled attack characteristic is desired, a current can be switched through diode D to limit the attack of the Vpk signal. Other conventional peak detector structures may include active gain stages but nonetheless follows the basic principle of peak detector 30 of FIG. 4.
The conventional peak detectors, such as peak detector 30, have several disadvantages. First, the attack and decay characteristics of the peak detector are determined by the discrete time constants of the resistors and the capacitors in the circuit. Because the electrical characteristics of the resistors and capacitors can vary with the fabrication process and the operating temperature, the charge and discharge rate of capacitor Cap can vary as a result which adversely affects the detector performance. Second, when the conventional peak detector is constructed as an integrated circuit, it is not practical to implement long time constants due to the large physical size of the capacitors and resistors or the noise level associated with operating the peak detector at extremely low current levels. Lastly, it is difficult to change the attack and decay characteristics in the conventional peak detector structure because doing so will consume more silicon real estate in an integrated circuit as multiple redundant devices are required. Thus, the manufacturing cost for the detector will increase while the yield may suffer.
Therefore, it is desirable to provide a peak detector which avoids the shortcomings of the conventional peak detector and it is further desirable to provide a peak detector whereby the attack and decay characteristics can be adjusted without requiring large increase in silicon area.
According to one embodiment of the present invention, a peak detector for detecting a peak voltage value of an input signal includes a first switch coupled to receive the input signal and selectively coupling the input signal to an input rectifier where the input rectifier generates a rectified input signal on a first node, a first charge storage device coupled between the first node and a ground node for storing a peak voltage value of the rectified input signal, and a second switch coupled between the first node and a second node for selectively coupling the first charge storage device to the second node. The peak detector further includes a third switch coupled between a reference potential and a second charge storage device for selectively discharging the second charge storage device to the reference potential, a fourth switch coupled between the second charge storage device and the second node, and a third charge storage device coupled between the second node and the ground node where the third charge storage device has a charge storage capability greater than that of the first and second charge storage devices. In operation, the first switch and the second switch are alternately closed to sample the input signal and generate an output voltage at the second node indicative of the peak voltage value of the input signal. Furthermore, the third switch and the fourth switch are alternately closed to decrease the output voltage at the second node.
According to one aspect of the present invention, the charge storage devices are capacitors. The peak detector of the present invention can implement asymmetrical attack and decay characteristics by selecting the appropriate capacitor ratios of the capacitors or by selecting the appropriate switching rates of the switches.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.